The student will support the CMOS+X project by developing and refining an AI-assisted framework for discovering new and better-performing circuits. The framework uses CaDRO for device sizing and SteerGenSE for circuit structure exploration. Working with UIC and Argonne researchers, the student will implement and evaluate search algorithms, improve circuit-generation models, develop robust simulation testbenches, and benchmark candidate designs using Spectre and foundry device models. The work will emphasize cryogenic readout and control circuits, including low-dropout regulators, voltage-controlled oscillators, and switching regulators. It will address performance, stability, power, and reliable operation at 4 K. The student will also help make the framework portable across partner sites and produce reproducible circuit netlists, performance summaries, and documentation for designers.
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Job Type
Part-time
Career Level
Intern
Education Level
No Education Listed