VHDL RTL Digital Logic Engineer
About The Position
Schweitzer Engineering Laboratories (SEL) is hiring a Hardware Engineer focused on VHDL Register-Transfer Level (RTL) digital logic for its R&D Communications product group. The role develops and supports Ethernet Security Gateways, Satellite Synchronized Network Clocks, Ethernet Switches, and other communication products used in critical infrastructure. The engineer designs and codes VHDL RTL digital logic for FPGA systems; prepares design specifications and internal documentation; and develops test plans and test harnesses or stimulus for functional verification. The position also involves participating in design, documentation, and test-plan peer reviews, maintaining project plans and labor estimates, collaborating with product managers and cross-discipline teams on new product concepts and enhancements, and applying SEL’s values and operating principles. The role is based at SEL’s corporate office in Pullman, Washington.
Requirements
- A bachelor's degree in Electrical Engineering, a related discipline, or an equivalent combination of education and experience.
- At least 2 years of combined experience in at least two of the following areas: FPGA RTL digital design using VHDL or Verilog; FPGA tools from Xilinx, Intel (Altera), Microchip (Microsemi/Actel), or Lattice Semiconductor; firmware design with FPGA SoCs or microprocessors using C/C++; simulation, synthesis, and timing analysis of digital logic; or functional verification of RTL digital logic.
- Ability to work cooperatively in a team environment.
- Ability to rapidly learn new skills and assume new responsibilities.
- Strong writing, technical documentation, and speaking skills.
Nice To Haves
- Experience in RTL, hardware, and firmware development practices.
- Knowledge of networking and Ethernet (IEEE 802.3).
- Knowledge of precise timing technologies such as PTP (IEEE 1588) and IRIG-B.
- Passion for designing RTL digital logic for FPGAs and solving difficult problems with efficient, creative solutions.
Responsibilities
- Analyze, design, and code VHDL RTL digital logic for FPGA systems.
- Create and maintain internal RTL design documentation.
- Write test plans and develop test harnesses and stimulus for RTL functional verification.
- Prepare design specifications.
- Participate in peer reviews of designs, documentation, and test plans.
- Provide and maintain accurate project plans and labor estimates.
- Work with product managers on new product concepts and enhancements.
- Engage with cross-discipline teams to deliver products for critical infrastructure.
- Apply SEL Values, Principles of Operations, and World Class Manufacturing Principles.
- Perform other duties as assigned.
Benefits
- Employer-funded employee stock ownership plan (ESOP) and personal 401(k) options.
- Medical, prescription, dental, vision, life, and disability insurance.
- 10 paid holidays.
- Annual vacation accrual starting at 12 days.
- 9 paid sick days.
- Paid family and medical leave covering 90% of pay.
- STEM courses, apprenticeships, tuition assistance, and engineering development programs.
- Wellness, fertility, adoption, and flexible spending benefits.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
