Verification Platform Engineer, Platform Architecture

Apple • Cupertino, CA

4d

About The Position

Apple’s Platform Architecture group develops the next generation of Apple hardware and the tools to make it possible. Our team builds high-performance verification systems that accelerate the development of Apple silicon. We aim to push the boundaries of pre-silicon validation with simulation solutions that apply and extend principles from hardware emulation.

This role bridges Apple's next-generation platform technology with DV methodology and tooling. We are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping solutions. In this role, you will enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
• Experience with SystemVerilog and EDA tooling.
• Experience with software development (e.g., using C++) and scripting (e.g., Perl or Python).

Nice To Haves

• Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field.
• 3+ years of relevant experience.
• Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture).
• Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows.
• Strong understanding of SystemVerilog simulation semantics (events, time, glitches); intuitive grasp for hardware representation (clocks, resets, latches).
• Strong communication skills, with a proven history of cross-functional collaboration across silicon engineering, design verification, and EDA development teams and organizational boundaries.
• Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration / emulation.
• Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers.

Responsibilities

• Enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior