About The Position

The CPU Platform Architecture team advances single-threaded and multi-threaded CPU performance to enhance the user experience across Apple products. The team includes experts in microarchitecture, ISA definition, performance and power modeling, and workload analysis. This role supports advanced exploration for next-generation iPhone, iPad, Mac, and server CPU designs. As a CPU Performance Engineer focused on the memory subsystem, you will help define and optimize CPU and cache microarchitecture. You will identify performance bottlenecks and evaluate potential improvements, collaborating with CPU and SoC designers in microarchitecture and RTL to assess ideas through modeling, refine ideas and model correlation, and develop new concepts. The role involves analyzing single-threaded and multi-threaded workloads across existing and new product categories to find bottlenecks and improvement opportunities. You will also work with the broader CPU architecture and performance team to maintain and improve the simulation environment, enabling data-driven decisions and increasing team productivity.

Requirements

  • Bachelor of Science degree.
  • Experience in CPU and SoC architecture and microarchitecture.
  • Experience with performance simulation environments.
  • Object-oriented programming experience in C/C++.
  • Experience in a scripting language such as Perl or Python.

Nice To Haves

  • Knowledge of memory latency tolerance techniques or other aspects of the CPU memory subsystem, such as prefetching and caching policies.
  • At least 3 years of relevant industry experience.
  • Master’s or PhD in Electrical or Computer Engineering or Computer Science.
  • Understanding of common data structures and algorithms.
  • Familiarity with SIMD, vector, or accelerator architectures.
  • Familiarity with multiprocessor performance.
  • Comfort working in an environment of uncertainty and navigating ambiguity.
  • Experience in a research-driven environment.

Responsibilities

  • Define and optimize CPU and cache microarchitecture, with a focus on the memory subsystem.
  • Identify performance bottlenecks and evaluate ideas to address them.
  • Collaborate with CPU and SoC designers in microarchitecture and RTL to assess the feasibility of ideas through modeling.
  • Refine ideas and model correlation, and seed new ideas.
  • Analyze single-threaded and multi-threaded workloads across existing and new product categories to identify bottlenecks and opportunities for improvement.
  • Collaborate with the CPU architecture and performance team to maintain and improve the simulation environment.
  • Support data-driven decisions and seek ways to improve team productivity.
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