Technical Staff Engineer - Layout

Microchip•Allentown, PA

About The Position

The job description identifies the role as Principal Engineer – Layout. As a member of Microchip’s engineering community, this engineer leads and executes automated place-and-route activities from floorplanning through GDSII tapeout. The role uses advanced physical design expertise and automation to improve productivity, optimize design flows, and develop physical design methodologies. The engineer collaborates with cross-functional engineering teams to address complex physical design challenges, improve design quality and efficiency, and support project execution through design signoff and tapeout.

Requirements

10+ years of experience in automated place and route and physical design.
Strong experience using industry-standard physical design tools and methodologies.
Strong scripting and automation skills using Tcl (preferred), Perl, Python, and shell scripting.
Demonstrated experience developing custom physical design utilities and methodology enhancements to improve efficiency and productivity.
Extensive experience with floorplanning and partitioning, power planning and power integrity, placement and routing optimization, clock tree synthesis, timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff, including LEC/CLP checks.
Strong analytical and problem-solving skills, including the ability to identify opportunities for flow optimization and methodology improvements.
Excellent oral and written communication skills and the ability to collaborate across engineering teams.
Self-motivated, proactive team player able to work independently, manage priorities, and deliver results according to project schedules and tapeout requirements.

Responsibilities

Lead and execute automated place-and-route activities from floorplanning through GDSII tapeout.
Use physical design expertise and automation to improve productivity and optimize design flows.
Develop physical design methodologies and automation solutions for timing and design closure, data extraction and analysis, QoR monitoring, ECO automation, and physical verification analysis.
Perform physical design activities including floorplanning and partitioning, power planning and power integrity, placement and routing optimization, clock tree synthesis, timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff, including LEC/CLP checks.
Collaborate with cross-functional engineering teams to solve physical design challenges and improve design quality and efficiency.
Support project execution in accordance with project schedules and tapeout requirements.