Staff Layout Designer

Micron•San Jose, CA

About The Position

The Staff Layout Designer will develop and prepare multi-dimensional layouts and create detailed semiconductor device drawings from schematics and geometry supplied by design engineers. The role includes verifying data integrity and leading major block developments. The designer will work with functional groups across global sites, including technology development, design, verification, and CAD teams, and should be able to learn quickly and adapt to changing priorities. The position contributes to the development of non-volatile memory products, with a focus on product performance, reliability, and power. It also involves technical and group contributions, mentoring junior team members, improving layout efficiency through automation and new methodologies, and planning and delivering major blocks and product revisions.

Requirements

Associate degree in Electronics, Electrical Engineering, or a related field, plus 10 years of direct experience in semiconductor layout design.
Deep working knowledge of EDA tools such as Cadence Virtuoso, Synopsys, and Calibre.
Ability to debug problems through root-cause analysis, identify effective and efficient solutions, and collaborate with engineering staff.
Skill in developing and applying custom layout, floor-planning, signal-planning, and power-planning methodologies.
Strong verbal and written communication skills.
In-depth understanding of design rules and delivery of quality layouts.
Strong physical verification analysis and debugging skills.

Nice To Haves

15 or more years of direct experience in semiconductor layout design.
Bachelor's degree in a related field.
Project leadership experience in quality optimization and die size shrinkage.
IC layout design experience with NAND, DRAM, and/or SRAM.
Understanding of Claude or Agentic AI, or willingness to learn and help develop efficient workflows.
Programming skills and AI experience relevant to layout workflows.

Responsibilities

Organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution.
Contribute to group management and technical innovation.
Assign resources, schedule tasks, provide direction, and deliver quality-controlled results.
Contribute to projects in a globally distributed design and layout environment.
Mentor junior team members.
Improve layout efficiency through automation and new methodologies.
Lead, plan, and deliver major blocks and product revisions.
Develop and prepare multi-dimensional layouts and detailed semiconductor device drawings from schematics and geometry provided by design engineers.
Verify data integrity and communicate with functional groups across global sites.