Technical Staff Engineer - Layout

Microchip Technology Inc.•Allentown, PA

About The Position

As a member of Microchip’s engineering community, the Principal Engineer – Layout leads and executes automated place-and-route activities from floorplanning through GDSII tapeout. The role uses advanced physical design expertise and automation capabilities to improve productivity, optimize design flows, and develop physical design methodologies. The Principal Engineer works with cross-functional engineering teams to solve complex physical design challenges, improve design quality and efficiency, and support project execution through design signoff and tapeout.

Requirements

10+ years of experience in automated place and route and physical design.
Strong experience using industry-standard physical design tools and methodologies.
Strong scripting and automation skills using Tcl, Perl, Python, and shell scripting; Tcl is preferred.
Demonstrated experience developing custom physical design utilities and methodology enhancements.
Extensive experience with physical design activities, including floorplanning and partitioning, power planning and power integrity, placement and routing optimization, Clock Tree Synthesis (CTS), timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff, including LEC/CLP checks.
Strong analytical and problem-solving skills, including the ability to identify opportunities for flow optimization and methodology improvements.
Excellent oral and written communication skills and the ability to collaborate across engineering teams.
Self-motivated and proactive team player able to work independently, manage priorities, and deliver results in accordance with project schedules and tapeout requirements.

Responsibilities

Lead and execute automated place-and-route activities from floorplanning through GDSII tapeout.
Use automation to drive productivity improvements, optimize design flows, and develop physical design methodologies.
Collaborate with cross-functional engineering teams to solve complex physical design challenges.
Improve design quality and efficiency and support project execution through design signoff and tapeout.
Develop custom physical design utilities and methodology enhancements to improve efficiency and productivity.
Develop automation solutions for timing and design closure, data extraction and analysis, QoR monitoring, ECO automation, and physical verification analysis.
Perform physical design activities including floorplanning and partitioning, power planning and power integrity, placement and routing optimization, CTS, timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff, including LEC/CLP checks.