Summer Intern - Formal Verification

Cirrus LogicAustin, TX
6dOnsite

About The Position

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! Cirrus Logic is seeking a Summer 2026 intern candidate for our Formal Verification team in Austin, TX. This position is focused on applying Formal Verification to digital designs. It is available to students currently enrolled in a MS or PhD program in Electrical and Computer Engineering. Candidate must be available for full-time employment during the internship.

Requirements

  • Master’s or PhD degree in Electrical or Computer Engineering
  • Knowledge in designing and implementing verification environments for module-level designs.
  • Excellent communication skills and a collaborative approach to working with team members.
  • Proficiency in System Verilog.
  • Familiarity with scripting languages such as Python, Perl, TCL, Bash.
  • Experienced or knowledge in UVM or equivalent methodologies.
  • Knowledge in formal property languages such as SVA.
  • Knowledge in property-based model-checking.
  • Knowledgeable in signal processing, analog or digital design fundamentals.

Responsibilities

  • Support the formal verification team to follow, and improve, defined methodology practices.
  • Develop test plans and verification methodologies to formally verify the microarchitecture and design.
  • Perform failure analysis and resolution, coverage analysis, and population.
  • Implement and improve functional and formal verification.
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