Formal Verification Engineer

ChipAgents•San Jose, CA

23h•$150,000 - $350,000•Onsite

About The Position

ChipAgents is revolutionizing chip design and verification with agentic-AI workflows. Founded by experts in AI and semiconductor design, we partner with top-10 semiconductor companies, hyperscale cloud providers, and cutting-edge startups. Our platform accelerates RTL development, functional verification, and simulation—unlocking new levels of productivity and design quality. We are seeking a highly capable Formal Verification Engineer to join our core product and research team. In this role, you will work closely with our AI engineering, research, and EDA teams to build advanced agentic AI systems for semiconductor verification. Your expertise in formal methods, property specification, assertion-based verification, and proof debugging will help shape how AI systems reason about complex hardware behavior. You will play a central role in teaching our AI agents how verification engineers develop properties, analyze counterexamples, close proof convergence gaps, and validate RTL designs with mathematical rigor. This is a unique opportunity to apply deep formal verification expertise at the frontier of AI-assisted chip design.

Requirements

Strong expertise in formal verification methodologies and signoff flows.
Hands-on experience with JasperGold, VC Formal, Questa Formal, or equivalent tools.
Deep knowledge of SystemVerilog Assertions (SVA) and assertion-based verification.
Experience proving complex properties, debugging counterexamples, and achieving formal closure.
Familiarity with SAT/SMT-based reasoning and formal verification fundamentals.
Experience with CDC, RDC, lint, and static verification methodologies.
Strong RTL design and microarchitecture understanding.
Experience verifying production IPs, subsystems, or SoCs.
Proficiency in Python, Tcl, or scripting for verification automation.
Interest in applying AI/LLMs to hardware design and verification workflows

Responsibilities

Collaborate with AI engineers and researchers to model and codify formal verification workflows.
Develop, refine, and debug SystemVerilog Assertions, formal properties, assumptions, constraints, and coverage objectives.
Use formal verification tools to analyze RTL designs, prove design correctness, and identify functional bugs.
Create reusable formal verification examples, design patterns, proof strategies, and edge cases to train and evaluate AI agents.
Help AI systems interpret design specifications, generate properties, reason about RTL behavior, and debug counterexamples.
Support benchmarking and evaluation of AI-assisted formal verification productivity across realistic IP and SoC verification tasks.
Work closely with customers, product, and research teams to translate formal verification pain points into automated AI workflows.
Contribute to methodology development for assertion-based verification, formal apps, equivalence checking, connectivity checking, and coverage closure.