Formal Verification - DV

Etched • San Jose, CA

2d • Onsite

About The Position

Etched is seeking a Formal Verification Engineer to join their ASIC Design Verification team. The role involves driving formal verification for custom IP, interface IP, and SoC subsystems within their ASICs. This includes compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers. The engineer will collaborate with architects, RTL designers, DV engineers, emulation teams, and software/firmware teams to ensure design correctness, identify corner-case bugs, and enhance verification closure across the entire chip.

Requirements

• 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon.
• Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
• Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
• Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
• Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.
• Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports.
• Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams.
• Thrive in a fast-paced startup environment and can take ownership of ambiguous, high-impact verification problems.

Nice To Haves

• Formal verification of systolic arrays, DMA engines, NoCs, memory subsystems, arithmetic datapaths, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers.
• Protocol compliance checking, connectivity checking, register verification, datapath validation, reset verification, or deadlock/livelock analysis.
• Vendor IP integration, encrypted or black-box IP verification, VIP configuration, and contract-based verification around subsystem boundaries.
• Sequential LEC, floating-point or integer arithmetic proofs, cache coherency checks, interrupt handling, or memory-mapped IO verification.
• Scripting in Python, TCL, Perl, or similar for automation, regression management, debug, and dashboarding.

Responsibilities

• Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
• Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
• Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
• Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.
• Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria.
• Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up.
• Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis.
• Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices.

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed