We are seeking a Member of Technical Staff, Senior Formal Verification Engineer. In this role, you will be responsible for developing and executing formal verification strategies and techniques to ensure design correctness. You will collaborate closely with Architects, RTL Design and Verification Engineers to understand the requirements, develop formal verification infrastructure and drive closure on the critical design blocks. You will be part of an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The work involves learning advanced LLM in modern data centers and applications to design memory acceleration. The ideal candidate possesses strong expertise in formal verification methodologies, SystemVerilog assertions (SVA), RTL design concepts and industry standard formal verification tools. This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.
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Job Type
Full-time
Career Level
Senior