Standard Cell Design Methodology & Flow Engineer

Apple • San Diego, CA

4d

About The Position

Join a Digital Design Engineering group to develop and enable standard-cell design methodologies and flows. This highly visible role supports a processor design effort, working with custom digital circuits and library development to help deliver quality products. The position involves standard-cell library design in deep submicron technologies and collaboration across custom circuits, CAD, design, and technology teams.

The engineer will coordinate production-flow planning with the internal CAD team and address PDK requirements with the foundry. They will collaborate with the technology team on new process requirements, enable appropriate tools and flows, implement digital blocks in Verilog/SystemVerilog, and verify them through simulation or formal checking. The role also uses data analysis and potentially machine-learning models to examine circuit timing, power, and area trends and identify quality issues in large datasets.

Requirements

• Bachelor of Science degree.
• At least 3 years of relevant industry experience.
• At least 5 years of experience in library characterization, timing/power/CCS noise and variation modeling, Liberty formats, SPICE simulation, and static timing and power analysis flows.
• Experience with timing modeling of large custom macros and complex sequential flops.
• Understanding of Design for Test and scan concepts, and ability to write DFT-friendly RTL.
• Understanding of implementation specifications, design, timing, power, and flow automation.
• Data-analysis and machine-learning knowledge for studying data trends and performing quality assurance on large datasets with automation.
• Flow-automation skills in standard-cell development and integration.
• Experience using Python, TCL, or Perl.
• Knowledge of FE modeling, Verilog and/or VHDL, and experience with EDA tools for characterization, synthesis, place-and-route, Verilog simulation, SPICE simulation, formal verification, DRC/LVS, RC extraction, and/or library characterization.
• Proven understanding of device physics and process.
• Familiarity with the foundry ecosystem and benchmarking practices.

Responsibilities

• Serve as the interface to the internal CAD team for production-flow planning and to the foundry for PDK requirements.
• Collaborate with the technology team on new process requirements and work with design and CAD teams to enable relevant tools and flows.
• Implement digital blocks in Verilog/SystemVerilog and verify them using simulation or formal checks.
• Use data analysis techniques and/or machine-learning models to study timing, power, and area trends and potentially detect quality issues in large datasets.
• Automate standard-cell development and integration flows to improve execution efficiency.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level