Standard Cell Design Methodology & Flow Engineer

Apple • San Diego, CA

3h

About The Position

Join a Digital Design Engineering group working on processor design in deep submicron technologies and standard cell libraries. In this role on the custom circuits team, you will work with the library development, technology, design, and CAD teams to plan and enable production flows, address process requirements, and help deliver quality products quickly. You will implement digital blocks in Verilog/SystemVerilog and verify them through simulation or formal checks. You may also apply data analysis techniques or machine-learning models to assess circuit timing, power, and area trends and identify quality issues in large datasets.

Requirements

• Bachelor of Science degree.
• At least 3 years of relevant industry experience.

Nice To Haves

• At least 5 years of experience in library characterization, timing/power/CCS noise/variation modeling, Liberty formats, SPICE simulation, and static timing and power analysis flows.
• Experience with timing modeling of large custom macros and complex sequential flops.
• Exposure to Design for Test, scan concepts, and writing DFT-friendly RTL.
• Understanding of implementation specifications, design, timing, power, and flow automation.
• Data analysis and machine-learning knowledge for studying data trends and performing automated QA on large datasets.
• Flow automation skills in standard-cell development and integration to improve execution efficiency.
• Experience using Python, TCL, or Perl.
• Knowledge of FE modeling, Verilog, and/or VHDL.
• Experience with EDA tools for characterization, synthesis, place-and-route, Verilog simulation, SPICE simulation, formal verification, DRC/LVS, RC extraction, and/or library characterization.
• Understanding of device physics and process.
• Familiarity with the foundry ecosystem and benchmarking practices.

Responsibilities

• Serve as the interface to the internal CAD team for production-flow planning and to the foundry for PDK requirements.
• Collaborate with the technology team on new process requirements and work with design and CAD teams to enable relevant tools and flows.
• Implement digital blocks in Verilog/SystemVerilog and run simulations or formal checks for verification.
• Use data analysis techniques and/or machine-learning models to study timing, power, and area trends and potentially detect quality issues in large datasets.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level