Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology

Samsung Electronics•Austin, TX

6d•$180,200 - $270,400

About The Position

Samsung’s SARC/ACL is building an Intellectual Property center of excellence for high-performance computing devices across mobile, automotive, and other custom markets. The DTCO Engineer will join the Global Advanced Technology Enablement team, which works with foundry partners from early stages of technology development to explore technologies for next-generation SoC products. The role develops efficient design and analysis flows and methodologies for DTCO, and collaborates with IP development teams to ensure process technology, design rules, standard-cell design, and methodology changes can be used throughout the product development cycle. The engineer will develop automated CAD flows and methodologies for custom design, explore approaches to meet low-power and high-performance goals for Samsung-specific SoC design styles, and help improve PPA and remove design bottlenecks. The position involves cross-functional collaboration, technical communication, documentation, publishing results, and driving solutions through to production. The team focuses on DTCO/technology enablement for advanced technologies beyond 5nm, aiming to improve product PPA, silicon reliability, and design turnaround time. The role provides exposure to multiple stages of development and work that may be incorporated into end-user products.

Requirements

At least 10 years of experience with a bachelor’s degree in Computer Science or Engineering; or at least 8 years with a master’s degree; or at least 6 years with a Ph.D.
At least 10 years of custom design tools and methodology development experience.
At least 10 years of experience with industry-standard automated design tools for synthesis, place and route, EM/IR analysis, static timing analysis, and/or physical verification.
Experience with Cadence Innovus and/or Synopsys Fusion Compiler and reference flows.
Experience with PPA analysis across standard-cell libraries, memory compilers, interconnect stack options, and block-level PPA evaluation.
Strong knowledge of CMOS fundamentals, device physics, device-technology interactions, scaling trends, and design and implementation challenges at advanced technology nodes.
Experience with batch-run-oriented environments for design-space exploration and high throughput.
Strong scripting and programming skills in languages such as Tcl, Perl, and Python.
Strong data analysis skills, including analyzing large datasets, drawing conclusions, and applying findings to other scenarios.
Ability to collaborate across teams and communicate technical requirements and specifications clearly.
Ability to maintain detailed documentation and drive solutions in a production- and results-oriented environment.

Nice To Haves

Experience working with foundries.
Experience improving productivity, efficiency, or quality of results through machine-learning practices.

Responsibilities

Build efficient design and analysis flows and methodologies for DTCO.
Develop highly automated CAD flows for custom design and continuously improve PPA on demanding designs.
Explore methodologies for achieving low-power and high-performance goals for Samsung-specific SoC design styles.
Apply expertise in digital design flows, including synthesis, place and route, EM/IR analysis, static timing analysis, physical verification, and large-design space exploration.
Collaborate with IP development teams to make process technology, design-rule, standard-cell, and design-methodology changes usable throughout the product development cycle.
Develop analysis methodologies and metrics to identify and remove design and CAD methodology bottlenecks.
Work with cross-functional stakeholders and communicate technical requirements and specifications clearly.
Maintain thorough documentation, publish results, and fulfill project-management-related needs.
Own problems and drive solutions toward production.
Support Foundry/EDA/Foundation IP development activities to unlock technology potential and improve PPA, silicon reliability, and design turnaround time.