Staff SoC Design Engineer

quadric•Burlingame, CA

15d•$170,000 - $230,000•Onsite

About The Position

Quadric is hiring a Staff SoC Design Engineer to contribute across all stages of its processor-based SoC design and integration cycle. The engineer will help define the SoC architecture, own subsystem development, integrate third-party IP, and optimize power, performance, and area (PPA) for the company’s next-generation platform. The role includes developing SoC subsystems and integrating IP such as NoC, PCIe/UCIe interfaces, DDR, and security components. The engineer will contribute to architecture decisions based on application requirements, package designs for customer releases, and iterate based on customer feedback. They will also develop SoC-level PPA strategies, apply low-power digital design techniques, contribute to timing closure from front-end through back-end and final tapeout, and balance single-stream latency with scaled throughput. Within the first 6–12 months, the engineer is expected to independently own SoC subsystem development, drive measurable PPA improvements, develop a thorough understanding of the architecture and software interfaces to debug issues across the software/hardware stack, and deliver packaged design releases for customer evaluation and integration. The position is based at Quadric’s downtown Burlingame office. Compensation includes a base salary range of $170,000–$230,000, equity, and a discretionary annual performance bonus as applicable to the role and level.

Requirements

Bachelor’s, master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
At least 5 years of hands-on SoC/ASIC front-end design and integration experience.
Proficiency in SystemVerilog or Verilog.
Strong background in computer architecture and low-power digital design techniques.
Deep technical knowledge in at least one subsystem: memory, I/O, or compute.
Experience with SoC subsystems, including third-party IP.
Working knowledge of VCS and Verilog/C co-simulation.

Nice To Haves

Experience in logic synthesis and performance modeling.
Experience in FPGA design.
Familiarity with automotive safety standards (ASIL) and hardware security standards.

Responsibilities

Own SoC-level subsystem development and integrate third-party IP, including components such as NoC, PCIe/UCIe interfaces, DDR, and security.
Contribute to SoC architecture definition by understanding application requirements.
Package designs for customer releases and iterate based on customer feedback.
Own SoC-level power, performance, and area (PPA) optimization strategies.
Apply low-power digital design techniques to improve hardware efficiency.
Contribute to timing closure across front-end, back-end, and final tapeout stages.
Balance single-stream latency with scaled throughput performance.
Debug complex issues across the software and hardware stack.
Deliver design releases for customer evaluation and integration.

Benefits

Medical, dental, and vision insurance from day one, with premiums covered at 99% for employees.
Company-paid life insurance.
Voluntary supplemental life insurance.
Short-term and long-term disability insurance.
Commuter support, including parking or Caltrain reimbursement.
Flexible spending account (FSA) and health savings account (HSA).
Equity.
Paid parental leave.
401(k) retirement plan.
Flexible PTO.
Winter holiday shutdown.
Catered lunch each day in the office.
Collaborative, low-ego culture with significant ownership and impact.