Staff Engineer, Digital ASIC Design — Storage Controllers

SK hynix memory solutions America Inc.•San Jose, CA

16h

About The Position

Join SK hynix Memory Solutions’ digital ASIC design team to develop IP for next-generation SSD controllers and storage solutions. The role spans controller architecture, including host interfaces, on-chip interconnects, and back-end NAND subsystems. The engineer translates product requirements into microarchitecture specifications, implements RTL, and works with verification and physical design teams to deliver production-ready silicon. The work helps shape the performance, power efficiency, and scalability of future storage products, with potential opportunities involving computational storage, storage for AI workloads, and next-generation SSD architectures.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
Demonstrated experience independently owning complex digital ASIC blocks, with technical depth and judgment appropriate for a Staff Engineer.
Strong proficiency in synthesizable Verilog or SystemVerilog and synchronous digital design fundamentals.
Working knowledge of ASIC development flows, including simulation using VCS or an equivalent tool, lint, CDC analysis, logic synthesis, static timing analysis, and timing closure.
Ability to write clear microarchitecture specifications, debug complex design issues, and communicate effectively across design, verification, and physical design teams.

Nice To Haves

Experience designing PCIe or NVMe controller logic.
Experience with SSD controller architectures, NAND interfaces, or flash storage systems.
Familiarity with AXI protocols, on-chip interconnects, and high-throughput data movement.
Experience with CPU subsystems or UCIe interfaces.
Experience delivering ASIC designs through tapeout and supporting silicon bring-up, validation, or production debug.

Responsibilities

Own digital ASIC blocks from requirements and microarchitecture definition through RTL implementation, verification support, and silicon delivery.
Develop microarchitecture specifications documenting interfaces, data flows, design tradeoffs, and implementation details.
Write synthesizable Verilog or SystemVerilog RTL that meets functional, performance, power, and area requirements.
Run and resolve findings from RTL lint, clock domain crossing (CDC), and synthesis tools to improve design quality.
Collaborate with design verification engineers on verification plans, debug simulations using tools such as Synopsys VCS, and resolve functional issues.
Work with physical design and timing teams on timing constraints, critical-path optimization, and timing closure.
Lead design reviews, provide technical guidance to other engineers, and coordinate with cross-functional teams to meet project milestones.