Staff Design Verification Engineer – Coherent Interconnect

SiFive•Boston, MA

About The Position

SiFive is looking for a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs, with particular emphasis on CXL-related protocol behavior, bridge paths, and subsystem integration. This is a Staff Engineer individual-contributor role for a candidate who can independently own complex verification problems, define strong verification plans, identify risk early, and raise verification quality across the broader interconnect effort. In this role, you will work across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, QoS behavior, and subsystem behavior across multiple interfaces, with a strong focus on CXL-oriented verification scenarios.

Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7+ years of experience in ASIC or SoC design verification, with strong hands-on ownership of complex block- or subsystem-level verification problems appropriate for a Staff / T4 role.
Strong protocol knowledge in CXL and at least one of CHI, ACE, AXI, or similar high-performance interconnect standards.
Strong hands-on experience with SystemVerilog and UVM-based verification, including building reusable verification infrastructure for complex hardware subsystems.
Strong understanding of cache-coherent systems, on-chip interconnects, memory-subsystem behavior, and verification of ordering and flow-control semantics.
Experience creating test plans, assertions, coverage models, scoreboards, and debug workflows for complex hardware subsystems.
Strong debugging skills with the ability to root-cause issues across specification, RTL, and testbench layers.
Strong scripting and automation skills in Python or similar languages.
Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast-moving environment.

Nice To Haves

Direct experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs.
Experience with protocol-conversion or bridge-heavy subsystems, especially where CXL protocol behavior or adaptation is a major part of system validation.
Experience with formal verification, performance-oriented verification, or emulation / FPGA-assisted debug.
Experience mentoring other engineers and influencing verification quality beyond immediate ownership scope.
Familiarity with large subsystem integration challenges involving coherent traffic, ordering, arbitration, QoS, and error handling across multiple interface types.

Responsibilities

Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, with emphasis on CXL and related coherent interconnect flows.
Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, QoS, and error handling.
Define high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, ordering, credits, arbitration, latency-sensitive flows, and bandwidth-sensitive behavior.
Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality.
Analyze failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
Contribute reusable methodology, infrastructure, and automation improvements that benefit the broader horizontal interconnect verification effort, not just the block directly assigned to you.
Mentor engineers and help raise verification quality across the team through reviews, technical guidance, and stronger verification practices.