Senior Staff Design Verification Engineer

Marvell Technology•Toronto, ON

23h•CA$118,700 - CA$158,300

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. This is an existing vacancy. Your Team, Your Impact Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can Expect ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. He/She will be responsible for block and /or chip level verification. The responsibilities include but not limited to. Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications. Use and improve UVM DV environment Improve the design methodology and flow. Collaborate with Analog/DSP/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines. Provide the support to the product teams, for both pre and post silicon.

Requirements

Bachelor’s degree in Computer Engineering, Electrical Engineering and 6+ years of related professional experience
Master’s/PhD in Computer Engineering, Electrical Engineering and 4+ years of related professional experience
Good personal communication skills and team working spirit.
Hardworking and motivated to be part of a highly competent design team.
Good communication and leadership skills to work with a global team.
Must be proficient in the following skills: Fundamental concepts in digital logic design
Understand ASIC verification flows and methodologies
Verilog, SystemVerilog, UVM
UNIX Shell scripting (Csh, Bash)

Nice To Haves

Experience with VIPs
Formal verification
PCIe, UCIe protocol knowledge
Low power design
MATLAB and C/C++ based system simulation and evaluation
DSP function hardware implementation knowledge
Strong Perl and Python scripting

Responsibilities

Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
Use and improve UVM DV environment
Improve the design methodology and flow.
Collaborate with Analog/DSP/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
Provide the support to the product teams, for both pre and post silicon.