Senior Design Verification Engineer
About The Position
Join AMD At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Join AMD’s PCIe Verification team and help bring next-generation high-speed interconnect designs to life. In this role, you’ll work on leading-edge CPUs, GPUs, and accelerators, collaborating with architecture, IP design, PHY, firmware, and SoC teams. You will own the functional verification of PCIe controller, PCS, and PHY interface logic, ensuring first-pass silicon success on industry-leading technologies. THE PERSON: We’re looking for a detail-oriented verification engineer with strong debug instincts, communication skills, and the ability to work across RTL, testbench, and firmware boundaries. Success means being highly analytical, collaborative, and eager to dive deep into complex, protocol-heavy IP.
Requirements
- Verification experience with PCIe or other high-speed interconnect IPs (e.g., CXL, USB, Ethernet, UCIe)
- Hands-on experience in SystemVerilog and UVM (stimulus, functional coverage, SVA)
- Familiarity with high-speed SerDes/PHY concepts and PHY-to-controller interfaces (e.g., PIPE)
- Experience with bring-up activities such as link training, equalization, CDR
- Exposure to AI/ML for engineering productivity (using copilots for testbench coding, predictive analytics, MCP tools, or regression optimization)
Nice To Haves
- Experience with PCIe/CXL VIP or formal verification
Responsibilities
- Develop and maintain UVM-based testbenches and verification environments for PCIe IPs and subsystems
- Write directed and constrained-random tests, functional coverage, and SystemVerilog assertions for PCIe Gen1-7, CXL, and related protocols
- Debug RTL and testbench issues across simulation environments
- Drive functional and code coverage closure; analyze regression results and triage failures
- Collaborate with design, SoC, PHY, and firmware teams on specification reviews, bug fixes, and feature bring-up
- Contribute to verification methodology improvements, reusable VIP, and regression infrastructure
Benefits
- AMD benefits at a glance.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
