Senior Design Verification Engineer

Prodapt • Vancouver, BC

4d • Onsite

About The Position

Prodapt is the largest and fastest-growing specialized player in the Connectedness industry, recognized by Gartner as a Large, Telecom-Native, Regional IT Service Provider across North America, Europe and Latin America. With its singular focus on the domain, Prodapt has built deep expertise in the most transformative technologies that connect our world. Prodapt is a trusted partner for enterprises across all layers of the Connectedness vertical. Prodapt designs, configures, and operates solutions across their digital landscape, network infrastructure, and business operations – and craft experiences that delight their customers. Today, Prodapt’s clients connect 1.1 billion people and 5.4 billion devices, and are among the largest telecom, media, and internet firms in the world. Prodapt works with Google, Amazon, Verizon, Vodafone, Liberty Global, Liberty Latin America, Claro, Lumen, Windstream, Rogers, Telus, KPN, Virgin Media, British Telecom, Deutsche Telekom, Adtran, Samsung, and many more. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries across North America, Latin America, Europe, Africa, and Asia. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 30,000 people across 80+ locations globally.
We are looking for a Senior Design Verification engineer to verify ASIC/SoC designs using SystemVerilog/UVM, develop automated test environments, and drive bug closure throughout the development cycle for one of our clients in Sunnyvale, CA.

Requirements

• Strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and familiarity with simulation tools.
• Ability to analyze complex systems and troubleshoot issues effectively.
• Proficiency in programming languages such as Python, C/C++, or SystemVerilog for automation and test development.
• Excellent verbal and written communication skills to collaborate with cross-functional teams.
• B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
• Hands-on experience in Verilog, SystemVerilog, C/C++ based verification, and UVM methodology
• Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.
• Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle

Nice To Haves

• Experience in the development of UVM based verification environments from scratch
• Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Experience with verification of ARM/RISC-V based sub-systems or SoCs

Responsibilities

• Develop and implement verification plans that outline the testing strategy for new designs.
• Create and execute test cases, simulations, and scripts to validate designs against specifications.
• Work closely with design engineers, software developers, and other stakeholders to understand design requirements and ensure comprehensive verification coverage.
• Identify, analyze, and resolve design issues and bugs through systematic testing and debugging techniques.
• Maintain detailed documentation of verification processes, test results, and design changes.
• Contribute to the development of best practices and methodologies for design verification.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior