Design Verification Engineer, Staff

Marvell Technology•Santa Clara, CA

2d•$96,570 - $144,600•Onsite

About The Position

As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc. In this in-office role in Santa Clara, you’ll work day to day with an RTL engineer to verify their design. Their design is in Verilog; you’ll use System Verilog to debug. You’ll run simulations using Synopsys VCS or a similar program, and then debug as needed until the design meets required specifications. You’ll also work closely with DFT engineers who are working in parallel on your blocks. You’ll attend weekly staff meetings to go over what everyone is working on and update your progress or address any issues. As you take responsibility for larger blocks, you may have to present to a review committee and explain your test plan and test schedule for those larger blocks.

Requirements

Completed a Bachelor’s Degree in Electrical Engineering or Computer Engineering and have 2 to 3 years of related professional experience OR a Master’s Degree and/or PhD in those fields.
Coursework included some analog classes, Verilog or VHDL, basic circuits, and computer architecture.
Focus in VLSI or show projects in courses that directly relate to chip design.
Used a tool like Synopsys, Cadence, or Mentor to run simulations.
Can write and debug a testbench.
Comfortable working in a Linux environment.
Comfortable doing scripting with Python.
Extremely detail-oriented.
Work and communicate well with your team, keeping them in the loop about your progress, issues you encounter, and any deviations from the planned schedule.

Nice To Haves

Ready to iterate a design over and over again until it is refined completely.

Responsibilities

Verify all of the circuitry that goes inside our chips for the general market and for specific customers.
Verify that each design meets our customers’ specifications.
Work day to day with an RTL engineer to verify their design.
Use System Verilog to debug Verilog designs.
Run simulations using Synopsys VCS or a similar program.
Debug simulations as needed until the design meets required specifications.
Work closely with DFT engineers who are working in parallel on your blocks.
Attend weekly staff meetings to go over what everyone is working on and update your progress or address any issues.
Present test plans and test schedules for larger blocks to a review committee.