Staff/ Sr. Staff Design Verification Engineer - QGOV

Qualcomm•San Diego, CA

4d•$147,600 - $246,000•Onsite

About The Position

This role is for a Design Verification Engineer at Qualcomm Technologies, Inc. The engineer will be responsible for developing verification methodologies, test plans, and test benches for hardware building blocks, design macros, and standard interfaces. The position requires end-to-end ownership of verification tasks, including coding, simulation, and achieving coverage goals. The role also involves exploring innovative DV methodologies and developing and maintaining emulation environments. The position requires the candidate to be in San Diego full-time, 5 days a week, and applicants will be subject to a government security investigation and must meet eligibility requirements for access to classified information, including being a U.S. citizen eligible for a U.S. Government security clearance.

Requirements

5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture
5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows
Relevant experience of 5+ yrs in any of the mentioned domain - Design/Verification/ Implementation
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Must be a U.S. citizen and eligible to receive a U.S. Government security clearance
Need to be in San Diego full time, 5 days a week

Nice To Haves

Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.
Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
Good understanding of chip-level functional model building
Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C
Knowledge of Behavioral and Structural models and familiarity with simulation environments
Experience customizing and debugging make-based build flows and working with Xilinx’s Vivado tools
Experience with cm tools such as Git and Gerrit.
Experience in formal / static verification methodologies will be a plus
Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.
Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.
Experience with C/C++ DPI transactors and monitors.
Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc.
Experience with GLS, and scripting languages such as Perl, Python is a plus
Linux OS proficiency
Self-starter with strong initiative, discipline, motivation, and a focus on quality.
Team player and be flexible and open to a variety of task assignments within the team.

Responsibilities

Familiarity with RTL design in Verilog and System Verilog
Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.
Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc).
Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals
Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches
Develop and maintain emulation environment to collect metrics related to emulation environment.
Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors.
Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations.
Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.