Fabric Interconnect Design Verification Engineer

Microsoft•Raleigh, NC

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for powering Microsoft’s “Intelligent Cloud” mission by delivering the core infrastructure and foundational technologies for Microsoft's online businesses. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE designs, develops, manufactures, and packages Microsoft's state-of-the-art computer chips, such as Azure Cobalt. As Microsoft's cloud business grows, the ability to deploy new offerings and hardware infrastructure on time, in high volume, with high quality, and at the lowest cost is crucial. The CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving planning processes, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. This role is for a Fabric Interconnect Design Verification Engineer within the CSME team, focusing on customer-focused solutions and future technical implementations for managing and optimizing cloud infrastructure.

Requirements

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
2+ years of pre-silicon subsystem or IP verification experience.
Ability to meet Microsoft, customer and/or government security screening requirements.
Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Must provide proof of country of citizenship or US residency or other protected status for assessment of eligibility to access export-controlled information.
Citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

Demonstrated experience in verifying designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols
Understanding of cache coherency architectures and microarchitectures
Experience with verification for a full product cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking
Aptitude for writing scripts/software with industry standard languages like Python
Experience applying generative AI to day-to-day tasks
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Responsibilities

Own verification of complex flows at Fabric Interconnect or at block level
Learn about the design and interact with partner teams to define verification strategies and test plans
Develop UVM-based verification environments and run and debug simulations to drive quality
Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
Innovate to improve verification efficiency through methodologies or tools
Apply industry leading generative AI solutions to verification work
Coach and mentor others in your areas of expertise
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion