Staff Design Verification Engineer – Coherent Interconnect

SiFive•Boston, MA

About The Position

SiFive is looking for a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. In this role, you will own complex verification problems spanning coherent data movement, protocol correctness, ordering, quality-of-service behavior, and subsystem integration across multiple interface types. The scope aligns to the Interconnect horizontal area and the coherent interconnect subsystem, with adjacent responsibilities around protocol conversion, bridges, and integration behavior. This is a Staff individual-contributor role. We are looking for someone who can go beyond executing assigned tests and instead define strategy, identify gaps early, solve complex verification problems, and raise the quality bar for the broader verification effort.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7+ years of experience in ASIC or SoC design verification.
Strong hands-on experience with SystemVerilog and UVM-based verification.
Strong understanding of cache-coherent systems, on-chip interconnects, or memory-system verification.
Experience verifying complex protocol behavior such as ordering, flow control, backpressure, buffering, arbitration, and error handling.
Experience building reusable testbench components, assertions, coverage models, and debug infrastructure.
Strong debugging skills and ability to root-cause issues across specification, RTL, and testbench layers.
Ability to work effectively across architecture, design, and verification teams in a fast-moving environment.
BS/MS Degree in EE, CE or CS
5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification
Deep understand of computer architecture is desired
Experienced developer using Object Oriented Programing principles

Nice To Haves

Experience with coherent interconnects, NoCs, memory fabrics, or large subsystem integration.
Experience with one or more industry protocols such as AXI, CHI, CXL, UCIe, or similar high-performance interface standards.
Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.
Experience verifying protocol-conversion or bridge-heavy subsystems.
Familiarity with Python or other scripting languages used for DV infrastructure and automation.
Experience mentoring other engineers and raising team-wide verification quality.

Responsibilities

Own verification planning and execution for a scalable cache-coherent interconnect subsystem, from block-level verification through subsystem integration.
Develop and maintain robust verification environments, checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, and error handling.
Verify protocol adaptation and integration across multiple interface types and bridge paths, including conversion, buffering, deinterleaving, and related data movement behaviors.
Drive verification of advanced interconnect behaviors such as QoS handling, arbitration policy, virtual-network behavior, and transport-level correctness.
Define high-value directed and constrained-random test scenarios that expose corner cases in coherency, concurrency, ordering, credits, and integration.
Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
Analyze failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
Improve verification methodology, infrastructure, and productivity for the broader interconnect verification effort, not just the block immediately assigned to you.
Contribute to review quality across specs, verification plans, coverage closure, and debug strategy.