Interconnect Design Engineer

SiFive•Boston, MA

About The Position

SiFive is looking for a staff level hardware engineer who is passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly-configurable generators. We leverage technology and ideas from the software industry to execute hardware design with the agility of software development. We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language, and are seeking motivated individuals to enhance/evolve our existing IP as well as develop new IP.

Requirements

Knowledge of cache and cache coherency architectures and concepts
Experience with NoC or other interconnect fabrics
Familiarity with industry-standard bus protocols (AXI, AHB, APB, CHI)
Ability to architect solutions to connect bus fabrics of disparate protocols
Strong software engineering skills/background, including: Object-oriented, aspect-oriented, and particularly functional programming
Templated metaprogramming, in any language
Compiler infrastructures, particularly for domain-specific languages
Data modeling, particularly intermediate representations for optimizing or transforming compiler passes
Test-driven development, particularly ability to write adaptive unit tests
Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL
Attention to detail and a focus on high-quality design
Ability to work well with others and a belief that engineering is a team sport
BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience

Nice To Haves

Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software
Knowledge of RISC-V architecture
Experience with Git/Github, Jira, Confluence

Responsibilities

Architect, design and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel
Implement RTL generators such that elements self-configure to optimally connect to each other
Enhance future designs to provide higher performance, more efficient multi-core and multi-system coherence
Design extensive configurability in as a first-class consideration
Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans
Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design