Design Verification Engineer

Apple•Cupertino, CA

2h•$186,472 - $220,900•Hybrid

About The Position

Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do. This role is available in Cupertino, California and various unanticipated locations throughout the USA. The primary goal is to ensure a bug-free first silicon for part of the SoC/IP. This involves developing detailed test and coverage plans based on the micro-architecture, and creating a verification methodology suitable for the IP, ensuring a scalable and portable environment. The role also includes developing the verification environment with all its components, designing and executing feature verification plans, and developing block, IP, and SoC level test-benches. Progress tracking and reporting using metrics like bugs and coverage are also key responsibilities. Additionally, the role may involve developing a mixed-signal simulation environment and collaborating with the analog team.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering, Computer Science, or related field and 1 year of experience in the job offered or related occupation.
Using Verilog, System Verilog to create complex IC verification environment to simulate pre-silicon all possible use cases
Using C and C++ to create reference models of the design under test to accurately predict the behavior
Using digital design and verification to test the design and debug the failures
Using Computer Architecture to understand the use case of the soft IP cores and how it inter-operates with the various CPU sub-systems
Using scripting languages like PERL or Python to create executable scripts.

Responsibilities

Ensure a bug-free first silicon for part of the SoC/IP.
Develop detailed test and coverage plans based on the micro-architecture.
Develop verification methodology suitable for the IP, ensuring scalable and portable environment.
Develop verification environment, including all the respective components including stimulus, checkers, assertions, trackers, coverage.
Design and execute feature verification plans, including design bring-up, design verification environment bring-up, regression enabling, debug of the test failures.
Develop block, IP and SoC level test-benches.
Track and report design verification progress using a variety of metrics, including bugs and coverage.
Develop mixed-signal simulation environment and work closely with analog team to ensure overall bug-free mixed-signal designs.