Staff Engineer, ASIC Design Verification

Samsung Semiconductor•San Jose, CA

9h•$163,000 - $253,000•Onsite

About The Position

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions such as Custom HBM base die, AI accelerators. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production.

Requirements

BE (MS preferred) in Computer/Electrical Engineering or Computer Science with 10+ years working experience in ASIC verification preferred.
Experience in UVM
Strong language skills including C++, SystemVerilog
Experience in logic and SoC verification from planning to closure
Good understanding on verification flows and tools
Experience in UCIe, HBM controller, Memory DFT.

Nice To Haves

Experience in DDR and Custom HBM and related IP level and/or SOC level verification
Experience and/or knowledge of the emerging technologies (CXL, Computation in memory and storage, AI LLM accelerators etc.) in server memory and storage systems
Highly motivated with good verbal and written communication skills
Creativity in problem solving
You’re inclusive, adapting your style to the situation and diverse global norms of our people.
An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
Innovative and creative, you proactively explore new ideas and adapt quickly to change

Responsibilities

Participate in verification strategy and methodology definitions
Contribute in micro architecture specification and reviews
Responsible for the verification of modules/subsystems of AI accelerators
Architect test benches, create test plans, implement test bench components in UVM
Execute the verification per plan to the closure
Work closely with architects and design engineers to define verification requirements, and to close functional and code coverage targets.
Provide support in post silicon bring up and debug