STA Application Engineer

Cadence Design Systems•San Jose, CA

1d•$106,400 - $197,600

About The Position

At Cadence, the STA Application Engineer performs static timing analysis, glitch analysis, and noise analysis using the Tempus Signoff tool. The role executes and delivers timing analysis flows, engineering change order (ECO) flows, CAD tools, and methodologies. It works with R&D and customers to enable timing analysis and ECO flows, including for newer advanced technologies, and leads Tempus timing signoff campaigns at existing and new customers. The position also performs timing correlation, tool-feature benchmarking, constraints validation, and SPICE analysis across technology nodes and customer designs. It contributes to in-design timing ECO optimization solutions and automates flows using scripting languages. The role delivers technical training and seminars within Cadence and at customer sites.

Requirements

Basic knowledge of Place and Route, Clock Tree, RC Extraction, and UPF/CPF concepts.
Knowledge of scripting languages such as Perl, Tcl, or Python.

Responsibilities

Perform static timing, glitch, and noise analysis using Tempus Signoff.
Execute and deliver timing analysis flows, ECO flows, CAD tools, and methodologies.
Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, and distributed and concurrent STA flows.
Collaborate with R&D and customers to enable timing analysis and ECO flows, including for newer advanced technologies.
Perform timing correlation, tool-feature benchmarking, constraints validation, and SPICE analysis on technology nodes and customer designs.
Work on in-design timing ECO optimization solutions.
Execute and lead Tempus timing signoff campaigns at existing and new customers.
Automate flows using Perl, Tcl, and Python.
Deliver technical trainings and seminars within Cadence and at customer sites.