St Staff Engineer, Power Delivery

Qualcomm • Austin, TX

1d • $191,800 - $287,800

About The Position

As a Qualcomm Hardware Engineer specializing in On-Chip Power Delivery Network (PDN) Architecture, you will define, develop, and optimize power-grid architectures for advanced-node, high-performance SoCs. The role focuses on on-die power delivery and power-grid architecture, including topology, rail structure, PDN-aware floorplanning, on-die decoupling, bump connectivity, IR drop, dynamic voltage droop, electromigration, coupling, and advanced power-delivery technologies.

You will work closely with SoC Architecture, Physical Design, IP Design, Package/PI, and technology teams to develop scalable PDN solutions that meet performance, power, area, reliability, and routing requirements across advanced technology nodes. The role includes driving power-integrity closure and developing scalable extraction, modeling, simulation, signoff, and correlation methodologies.

The minimum qualifications allow a bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field with 6+ years of relevant experience; a master's degree in one of those fields with 5+ years; or a Ph.D. with 4+ years. The posted pay range is $191,800–$287,800. Qualcomm also describes a competitive annual discretionary bonus program, potential annual RSU grants, and a competitive benefits package.

Requirements

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field and 6+ years of System/Package Design/Technology Engineering or related work experience; OR a master's degree in one of these fields and 5+ years of relevant experience; OR a Ph.D. in one of these fields and 4+ years of relevant experience.

Nice To Haves

• Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field with a focus on power integrity, VLSI, physical design, or semiconductor power delivery.
• Deep expertise in on-chip power-grid architecture, PDN optimization, and advanced-node power delivery.
• Experience with Cadence Voltus, Sigrity PowerSI, Ansys HFSS/Q3D/SiWave, HSpice, ADS, or equivalent power-integrity and circuit-simulation tools.
• Experience developing or improving PDN extraction, modeling, analysis, automation, and signoff methodologies.
• Knowledge of advanced power-grid technologies, backside power delivery, advanced packaging, and die-to-package power-delivery co-optimization.
• Strong scripting and automation skills using Python, TCL, or similar languages.
• Demonstrated ability to work cross-functionally with SoC Architecture, Physical Design, IP, Package, PI, and technology teams.

Responsibilities

• Own on-chip power delivery network architecture and power-grid strategy for advanced-node, high-performance SoCs.
• Define and optimize power-grid topology, rail structure, power domains, grid architecture, and power/ground distribution for high-current CPU, NSP, GPU, and other performance-critical IPs.
• Drive PDN-aware floorplanning with SoC Physical Design and IP teams, optimizing power delivery while considering PPA, routing resources, timing, and implementation constraints.
• Define and optimize on-die power-grid connectivity to bump interfaces, including bump allocation and interaction between the on-die PG, package PDN, and decoupling capacitance.
• Define and optimize the on-die decoupling-capacitance strategy, including decap allocation, placement, and effectiveness across the applicable PDN frequency range.
• Establish static IR-drop, dynamic voltage-droop, impedance, EM/current-density, and reliability budgets for performance-critical power rails.
• Perform and drive static IR, dynamic voltage-drop, transient, impedance, EM, and PDN coupling analyses to achieve power-integrity closure.
• Co-optimize the on-chip power grid with floorplan, timing, PPA, routing resources, bump allocation, and package connectivity, particularly for advanced nodes with constrained routing resources.
• Define the on-chip PG roadmap for advanced technology nodes, including evaluation and tradeoff analysis of conventional front-side power grids, backside power delivery, and other emerging power-delivery technologies.
• Drive PGPOR roadmap and architecture tradeoff analysis, including power-grid architecture, rail structure, implementation options, and advanced PDN solutions.
• Partner with Physical Design, SoC Architecture, IP Design, Package/PI, and technology teams from early architecture and floorplanning through implementation and design closure.
• Develop scalable PDN extraction, modeling, simulation, signoff, and correlation methodologies to support advanced-node SoC development.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants; employees on sales-incentive plans are not eligible for the annual bonus.
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior