SPE Signal Integrity

Rambus•Johns Creek, GA

1d•$126,100 - $234,100•Hybrid

About The Position

Rambus is seeking a Sr. Principal Engineer with signal integrity and package design experience to join the Memory Interface Chips BU engineering team in John's Creek, Georgia. Reporting to the Senior Director of Engineering, this full-time role works within the SI/PI team on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) for DDR products operating at speeds up to 16000+ MT/s. The role follows a hybrid approach: employees are encouraged to work onsite an average of at least three days per week, with up to two days of remote work. The engineer will provide technical leadership in SI/PI and package design, develop methodologies, and collaborate with design, validation, and customer teams. The work includes system and package requirements, simulations, silicon correlation, and support for lab debug and bring-up. The position requires an advanced electrical engineering degree, substantial industry experience, and expertise in high-speed memory interfaces, signal-integrity analysis, and related simulation tools. Rambus is a global provider of memory interface chips and silicon IP. The company offers competitive compensation, including base salary, bonus, equity, matching 401(k), employee stock purchase plan, medical and dental benefits, a time-off program, and gym membership. The US salary range for this full-time position is $126,100 to $234,100; starting pay depends on job-related skills, experience, qualifications, work location, and market conditions. Rambus states its commitment to an inclusive workplace and equal employment opportunity.

Requirements

Solid background in SI/PI and package design, with the ability to provide technical leadership.
Strong interpersonal skills to keep the team motivated and focused.
MS or PhD in Electrical Engineering and 10+ years of industry experience, including at least a few years of exposure to DDR4/5.
Prior experience simulating high-speed memory (DDR4, DDR5) and/or SERDES interfaces.
Strong theoretical background and understanding of electromagnetics and transmission-line theory.
Strong background and understanding of equalization techniques such as FIR/FFE/DFE/CTLE.
Understanding of package and PCB design and ability to edit APD/Allegro layout files.
Knowledge of SI/PI-driven BGA assignment methodology and ability to simulate trade-offs in a system context.
Extensive experience correlating simulation results with lab measurements using scopes, TDRs, VNAs, and similar equipment.
Knowledge of server systems, from CPUs to DRAMs on DIMM modules, is required by the posting's qualifications section as a highly desirable capability.
Knowledge of crosstalk and jitter mechanisms in source-synchronous interfaces and ability to include the effects of losses in low-BER simulations.
Proficiency with Spice and ADS simulations.
Excellent writing, presentation, and communication skills for working with customers and cross-functional teams.
Innovative, self-motivated, able to manage and drive projects, and a team player.

Nice To Haves

Strong understanding of server systems, from CPUs to DRAMs on DIMM modules.
Familiarity with RedHawk/Totem or XcitePI and Virtuoso.
Lab characterization experience with passive components, link margin, or noise using real-time or sampling scopes and VNA/TDR.
Basic knowledge of circuits used in high-speed link design.

Responsibilities

Create SI/PI methodologies and work with Design and SI teams on SI/PI studies and package design for the DDR product portfolio.
Work with design and validation teams to define specifications and system design requirements, including packaging and PCB routing, IC-PKG-BRD decoupling requirements, channel simulations, and jitter sensitivity analysis.
Provide design guidelines based on SI/PI studies, simulations, and silicon correlation to support superior signal-integrity performance and RMT scores.
Collaborate with customers to identify optimum SI/PI solutions.
Help the team with debugging and lab bring-up when needed.