SPE Signal Integrity

Rambus•San Jose, CA

2d•$126,100 - $234,100•Hybrid

About The Position

Rambus is seeking a Senior Principal Engineer with signal integrity and package design experience to join the Memory Interface Chips BU engineering team in John's Creek, Georgia. The role works within the SI/PI team on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) for DDR products operating at speeds up to 16000+ MT/s. The position reports to the Senior Director of Engineering and is full-time. It follows a hybrid work approach, with employees encouraged to spend an average of at least three days per week onsite and up to two days working remotely. The engineer will provide technical leadership in SI/PI and package design, develop methodologies, collaborate with design, validation, and customer teams, and help debug and bring up products in the lab when needed.

Requirements

MS or PhD in Electrical Engineering.
10+ years of industry experience, including at least a few years of exposure to DDR4/5.
Prior experience simulating high-speed memory (DDR4, DDR5) and/or SERDES interfaces.
Solid theoretical background and understanding of electromagnetics and transmission-line theory.
Strong background and understanding of equalization techniques such as FIR, FFE, DFE, and CTLE.
Understanding of package and PCB design, including the ability to edit APD/Allegro layout files.
Knowledge of SI/PI-driven BGA assignment methodology and ability to simulate system-level trade-offs.
Extensive experience correlating simulation results with lab measurements using equipment such as scopes, TDRs, and VNAs.
Knowledge of crosstalk and jitter mechanisms in source-synchronous interfaces and ability to include the effects of such losses in low-BER simulations.
Proficiency with Spice and ADS simulations.
Excellent writing, presentation, and communication skills for working with customers and cross-functional teams.
Strong interpersonal skills and ability to keep a team motivated and focused.
Innovative, self-motivated, able to manage and drive projects, and a team player.

Nice To Haves

Strong understanding of server systems, from CPUs to DRAMs on DIMM modules.
Familiarity with RedHawk/Totem or XcitePI and Virtuoso.
Lab characterization experience with passive components, link margin, or noise using real-time or sampling scopes and VNA/TDR.
Basic knowledge of circuits used in high-speed link design.

Responsibilities

Create SI/PI methodologies and collaborate with Design and SI teams on SI/PI studies and package design for the DDR product portfolio.
Work with design and validation teams to define specifications and system design requirements, including packaging and PCB routing, IC-PKG-BRD decoupling requirements, channel simulations, and jitter sensitivity analysis.
Provide design guidance based on SI/PI studies, simulations, and silicon correlation to support superior signal integrity performance and RMT scores.
Collaborate with customers to identify optimum SI/PI solutions.
Assist the team with debugging and lab bring-up when needed.
Manage and drive assigned projects and work with customers and cross-functional teams.