Sr Director - DfT, Test Development, HW Roadmap

GlobalFoundries•Richardson, TX

22h

About The Position

GlobalFoundries is hiring a senior leader to direct DfT (Design-for-Test), test development, and ATE hardware design and roadmap work. The role leads a team of DfT, test, and ATE HW design engineers and defines and oversees implementation of test methods and technologies intended to deliver strong coverage and quality, high parallelism, and low cost of test across digital, analog, mixed-signal, memory (including NVM), HSIO, RF IPs, and SoCs. The position defines DfT and BiST methodologies, production test flows and insertion strategies, characterization requirements, and future ATE platform requirements based on product roadmaps. It also sets ATE hardware strategy for probe and final test, including the integration, validation, qualification, and factory buyoff of test-cell hardware. The role collaborates with design, DfT, product engineering, and factory teams to guide product development and improve processes and test methods. Familiarity with high-speed interfaces and their protocols and standards is important; the candidate is expected to learn applicable protocols, define high-volume parallel test methods, and develop ATE test plans for characterization and production testing.

Requirements

MSEE or BSEE.
15–20+ years of experience working in product or test.
At least 10 years of experience with DfT and BiST strategies across digital, RF, and analog/mixed-signal products.
At least 10 years of management experience.
Experience with ATE platforms and defining ATE roadmap solutions, including full test-cell definitions.
Track record of enabling and bringing multiple products and technologies into high-volume production.
Excellent communication and leadership skills, including work with cross-functional teams across internal development and factory sites.
Understanding of product financial metrics and terms, with a proven track record of driving cost-reduction activities.
Strong knowledge of factory operations, assembly, and test operations.
Good IC and test knowledge across digital, analog, and mixed-signal, including ATE platforms, DfT strategies, test methods, and instrumentation requirements for analog, mixed-signal, and digital tests.
Familiarity with protocols and industry standards for IPs, including high-speed interfaces and analog and mixed-signal circuits.
Prior experience with DfT and ATE test equipment for IC testing, and hands-on knowledge across digital, analog, and RF.

Nice To Haves

Knowledge of high-speed interfaces such as PCIe, LVDS, CSI, DSI, QSPI, DDR, HDMI, and USB; power management; massive multisite testing; and/or IPs requiring safety and security.
Project management skills, including the ability to innovate, execute on solutions, and navigate ambiguity.
Strong written and verbal communication skills.
Strong planning and organizational skills.

Responsibilities

Lead a team of DfT, test, and ATE hardware design engineers.
Define and oversee implementation of DfT and BiST methodologies and technologies aimed at strong coverage and quality, maximum multisite testing, and low cost of test across digital SoCs and IPs, NVM memories, HSIO, analog/mixed-signal, and RF products.
Drive test methods, test flows, and quality screens for various NVM memory types.
Define new ATE platforms and roadmap solutions to support products based on 5–10-year product roadmaps.
Define and develop Test Method Libraries to standardize test methods across products and ATE platforms.
Define DfT for both IPs and SoCs.
Develop ATE test plans for characterization and production testing, including high-volume testing with high parallelism.
Define production test flows across test insertions to achieve strong coverage and low cost of test.
Define process and silicon characterization requirements for NPDE teams during product validation and execution.
Set ATE hardware strategy for probe and final test, including integration, validation, qualification, and factory buyoff of ATE hardware solutions such as handlers, probers, and sockets.
Serve as liaison between BU PE and factory teams to validate hardware and software at factory-installed test cells, including temperature-test capabilities.
Identify and document gaps, best practices, and lessons learned, and provide feedback to Design, DfT, and PE NPDE/Cost Entitlement teams to improve future processes and test methods.
Work closely with cross-functional Design, Design DfT, and NPDE PE teams to direct, guide, and influence product development.
Perform work safely and support Environmental, Health, Safety & Security requirements and programs.