Design for Test (DFT) Engineer

Voltai • Palo Alto, CA

1d

About The Position

Voltai is developing world models and agents that learn, evaluate, plan, experiment, and interact with the physical world, beginning with hardware, electronics systems, and semiconductors. The Design for Test Engineer will ensure chips can be tested in manufacturing and in the field. The role owns DFT architecture and implementation on silicon programs with semiconductor companies and helps train Voltai’s AI in DFT methodology.

Requirements

• At least 5 years of DFT experience on production tapeouts.
• Hands-on experience with Tessent, TestMAX, or Modus.
• Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
• Experience with DFT verification and gate-level simulation.
• Tcl and Python scripting.

Nice To Haves

• Post-silicon test bring-up and ATE experience.
• Experience with 2.5D/3D or chiplet test strategies.
• Interest in AI-assisted design tools.

Responsibilities

• Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
• Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets.
• Work with RTL, synthesis, and physical design teams to close DFT timing and area impact.
• Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
• Build automation for DFT flows and coverage reporting.
• Help define how AI can accelerate DFT insertion and pattern generation.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed