Intern, Physical Design & DFT
About The Position
This is where verified RTL becomes an actual, manufacturable chip. Every timing constraint, every power tradeoff, every Design For Test (DFT) decision here determines whether the silicon works when it comes back from the fab. This posting spans multiple teams within Physical Design and DFT. One application, one recruiter screen — then we match you to the specific team and location that fits best. Teams include: Physical Design: Synthesis, floorplanning, place & route, clocking, timing closure. Advanced Physical Design: ML-assisted approaches to physical design flows. DFT: Design hardware to enable structural post-silicon test. JTAG, Scan/ATPG, MBIST.
Requirements
- Currently pursuing a BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, Software Engineering.
- Solid understanding of logic design, VLSI, and transistor-level concepts.
- Familiarity with PnR tools, timing analysis, and power optimization techniques.
- Familiarity with JTAG, MBIST, and scan concepts.
- Comfortable scripting in Tcl, Perl, Shell, or Python.
Nice To Haves
- Hands-on experience with a commercial PnR toolchain (Synopsys, Cadence).
- Coursework or projects in DFT, test methodology, VLSI or digital design, computer architecture.
- Interest or exposure with AI tools to accelerate development and workflows.
Responsibilities
- Synthesis
- Floorplanning
- Place & route
- Clocking
- Timing closure
- ML-assisted approaches to physical design flows
- Design hardware to enable structural post-silicon test
- JTAG, Scan/ATPG, MBIST
Benefits
- Highly competitive compensation package
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Intern
Education Level
No Education Listed
