Digital Design Engineer, DFT

Analog Devices • Dallas, TX

1d • Onsite

About The Position

As a key member of the team, he/she will be responsible for DFT specifications, architecture and implementation using state-of-the-art methodologies and tools. This role will support various product lines for DFT insertion and High Coverage, Low Power, Low Test Time scan patterns. Responsibilities also include pre/post silicon verification & debug, and the ability to work independently as well as in a team.

Requirements

• Masters of Science degree in Electrical Engineering, Computer Engineering or similar
• 2 years of directly related experience in ASIC/SoC DFT
• Good understanding of DFT architecture and planning
• Hands on scan insertion and ATPG Tool experience
• Hands on experience of DFT Compression Insertion, On-Chip Clock Control Insertion
• Hands on experience of Gate-level simulation with zero delay and SDF
• Good understanding of Failure Analysis
• Scripting: Perl/Python/Tcl
• Team-player: the ability to forge and maintain relationships with peer-organizations
• Strong written and verbal communication skills

Nice To Haves

• Experience with Tessent DFT tools
• Good understanding of IEEE 1149 and JTAG
• Experience with LBIST and MBIST
• Experience with advanced DFT technologies like low power, SSN, Fault Grading

Responsibilities

• DFT specifications, architecture and implementation using state-of-the-art methodologies and tools
• Support various product lines for DFT insertion
• Support various product lines for High Coverage, Low Power, Low Test Time scan patterns
• Pre/Post silicon verification & debug
• Work independently as well as in team

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level