DFT Engineer

Match Point Solutions • Menlo Park, CA

7d • $50 - $70 • Remote

About The Position

MatchPoint Solutions is a fast-growing, young, energetic global IT-Engineering services company with clients across the US. We provide technology solutions to various clients like Uber, Robinhood, Netflix, Airbnb, Google, Sephora, and more! More recently, we have expanded to working internationally in Canada, China, Ireland, UK, Brazil, and India. Through our culture of innovation, we inspire, build, and deliver business results, from idea to outcome. We keep our clients on the cutting edge of the latest technologies and provide solutions by using industry-specific best practices and expertise. We are excited to be continuously expanding our team. If you are interested in this position, please send over your updated resume. We look forward to hearing from you!

Requirements

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.
• Verilog / SystemVerilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.
• Scan Insertion: Hands-on experience with scan synthesis, compressed scan architectures (EDT/SmartTest), and boundary scan integration.
• ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
• MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
• JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
• Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.

Nice To Haves

• Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.
• Knowledge of advanced DFT concepts like High-Speed IO testing, SerDes loopback, or Analog DFT.
• Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes.

Responsibilities

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).
• Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.
• Integrate Memory BIST (MBIST) controllers, repair mechanisms, and custom memory test routines.
• Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including Stuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.
• Execute Verilog/SystemVerilog simulations for gate-level DFT validation, ensuring timing and vector cleanliness (SDF simulation).
• Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT, Tessent, Modus, or TetraMAX).
• Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) for ATE (Automatic Test Equipment) deployment.
• Support post-silicon bring-up in the lab, debugging first-silicon DFT features, pattern conversion, and silicon failures.
• Collaborate with Product and Test Engineering (PTE) teams to optimize test time, diagnose failure modes, and boost manufacturing yield.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed