ASIC Design Verification Engineer, DFT

Meta•Sunnyvale, CA

5h•$146,000 - $209,000

About The Position

Meta is hiring an ASIC Design Verification Engineer specializing in Design for Testability (DFT) within the Infrastructure Silicon organization. We are looking for experienced engineers to develop and verify DFT architectures for custom ASICs and System on Chip (SoC) designs powering Meta's data center infrastructure. In this role, you will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring silicon manufacturability, testability, and quality for first-pass success. You will collaborate closely with Design, DFT Architecture, Emulation, and Post-Silicon Validation teams to develop robust verification environments that validate scan, BIST, JTAG, and other DFT structures using simulation, formal analysis, and emulation-based methodologies.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of hands-on experience in ASIC design verification using SystemVerilog and UVM-based methodologies
6+ years of experience with DFT verification, including scan insertion, ATPG pattern validation, BIST verification, and JTAG/IEEE 1149.1 test access mechanisms
Experience with EDA tools for DFT insertion, ATPG, and simulation, along with scripting proficiency in Python, Tcl, Perl, or Shell for verification flow automation
Experience driving IP, sub-system, or SoC-level verification closure including test planning, testbench development, and coverage analysis

Nice To Haves

Experience with formal verification techniques applied to DFT control logic, scan enable paths, or test mode isolation
Experience verifying high-speed interface DFT structures such as PCIe, HBM, DDR, or Ethernet SerDes
Experience with DFT verification for AI/ML accelerator or networking ASIC designs in data center environments
Experience with emulation platforms for DFT bring-up and pre-silicon to post-silicon correlation

Responsibilities

Define and implement DFT verification plans covering scan insertion, ATPG, BIST, JTAG, and boundary scan structures at IP, sub-system, and SoC levels
Develop and maintain UVM-based and C/C++-based testbenches to verify DFT logic, including scan chains, memory BIST, and logic BIST controllers
Drive verification closure using defined metrics including functional coverage, code coverage, and DFT-specific structural coverage goals
Collaborate with DFT architects and design engineers to review DFT insertion methodologies and validate correctness of scan stitching and test access mechanisms
Debug and root-cause functional and structural failures in DFT logic, working closely with design and ATPG teams to resolve issues pre-silicon
Develop and validate ATPG test pattern generation flows, ensuring pattern quality and fault coverage targets are met
Apply formal verification techniques to prove correctness of DFT control logic, scan enable paths, and test mode isolation
Partner with emulation and post-silicon validation teams to enable DFT bring-up and correlate pre-silicon verification results with silicon test outcomes
Build and maintain verification infrastructure, scripts, and automation flows to improve DFT verification efficiency and reuse across projects
Contribute to continuous improvement of DFT verification methodologies, tools, and best practices across the infrastructure silicon team