Senior ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise•Fort Collins, CO
•$135,000 - $310,500•Hybrid

About The Position

This role focuses on the development of HPE Slingshot, an industry-leading interconnect for large-scale HPC and AI systems. The Senior Design Verification Engineer will collaborate with architects, logic designers, and other verification engineers on switch and NIC ASICs for future Slingshot generations. Key responsibilities include owning significant verification scope, setting technical direction for blocks or subsystems, and contributing to the application of emerging agentic AI workflows to complex engineering challenges. The ideal candidate is passionate about high-performance interconnects, enjoys mentoring, and seeks influence over verification methodology beyond just test writing.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
  • 10+ years of experience in VLSI design, verification, or implementation.
  • Expert level knowledge of SystemVerilog and of OVM or UVM methodologies.
  • Expert level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
  • Expert level analytical and problem solving skills.
  • Ability to excel in a distributed team environment.
  • Executive level written and verbal communication skills; mastery in English.

Nice To Haves

  • Experience verifying high-speed networking, switching, or NIC ASICs.
  • Experience with agentic AI coding tools and workflows applied to verification.
  • Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
  • Experience working as part of a geographically distributed team.

Responsibilities

  • Follow and help define the team's design verification methodology.
  • Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
  • Plan and implement block and integration level scoreboards and checkers to verify functional behavior.
  • Write and analyze functional coverage, providing input to block level milestones.
  • Triage regression failures and identify logic bugs, while driving bug closure.
  • Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.
  • Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.
  • Participate in and provide input on the process for selection of future technical leaders.
  • Drive VLSI innovation and integration of new technologies into projects and activities in the design organization.

Benefits

  • Health & Wellbeing benefits
  • Personal & Professional Development programs
  • Unconditional Inclusion
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