Sr. Design Verification Engineer

Micron • Minneapolis, MN

1d

About The Position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We build the verification foundation that ensures Micron’s most advanced ASICs work exactly as intended. Our ASIC Design Verification team develops robust, scalable verification environments for highly complex designs and partners closely with global design teams to deliver high‑quality silicon on schedule. If you enjoy tackling deep technical challenges, solving problems that matter, and leveraging modern tools—including AI‑assisted workflows—to work more effectively, this is the place to do it! As a technical member of the ASIC Design Verification team, you will play a critical role in validating complex SoC designs using modern verification methodologies. You will take end‑to‑end ownership of verification environments, collaborate closely with design and architecture teams, and help drive verification quality across Micron’s next‑generation memory products. You will also have opportunities to adopt and influence emerging AI‑based approaches that improve verification productivity, debugging efficiency, and quality.

Requirements

• Bachelor’s or Master's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience
• 6+ years of experience in IP or SoC verification
• Hands‑on experience with UVM and constrained‑random verification
• Strong proficiency in SystemVerilog and Python
• Exposure to microcode, assembly language, or firmware development
• Proven analytical, debugging, and communication skills

Nice To Haves

• Experience with mixed‑signal verification
• Experience with DRAM protocol
• Experience using or evaluating AI‑assisted development, verification, or debug tools
• Interest in applying AI/ML techniques to improve verification flows, automation, or productivity
• Experience working in fast‑paced, highly collaborative engineering environments

Responsibilities

• Develop and maintain UVM‑based SystemVerilog verification environments
• Define and execute block and system‑level verification plans
• Build and enhance Python‑based testbenches and simulation infrastructure
• Debug complex functional and integration issues in close collaboration with design teams
• Drive coverage closure and continuously improve verification quality metrics
• Explore and adopt AI‑assisted techniques and tools to improve verification productivity and debug efficiency

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time‑off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior