Design Verification Engineer

Baidu USA•Sunnyvale, CA

5d•Onsite

About The Position

We are looking for an experienced design verification engineer to join our SoC team at Baidu’s Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment. Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level. You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage. Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model. Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite. Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.

Requirements

Minimum 5 years of experience of UVM based verification on a significantly complex project.
Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
Advanced knowledge of System Verilog and the UVM methodology.
Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
Good practice of one scripting language (Perl, Python, Tcl) no preference.
SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
Familiar with C/C++.
Formal Verification (Model Checking, Equivalence Checking).
Excellent communication skills in both English and Chinese.

Responsibilities

Verify the functionality of Baidu's AI SoC at both block level and SoC level.
Develop UVM Testbench.
Perform directed/constrained random test generation.
Conduct failure analysis and resolution.
Perform coverage analysis.
Develop verification flow.
Run RTL and gate level functional verification.
Debug failures.
Lead bug tracking.
Analyze and close coverage.
Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Support mixed-signal co-simulation using Verilog models of analog IP.
Develop testbench, test cases, reference model, coverage model and automation of regression suite.
Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.