Design Verification Engineer

Apple

5h

About The Position

At Apple, we work to craft products that enrich people’s lives. We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture.

Requirements

• Minimum requirement of a bachelors degree
• BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent
• Deep knowledge of SystemVerilog and UVM
• Deep knowledge in developing scalable and portable test-benches
• Proven experience with verification methodologies and tools such as simulators, waveform viewers
• Build and run automation, coverage collection, gate level simulations
• C/C++ level knowledge
• Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
• Knowledge of one of the scripting languages such as Python, Perl, TCL

Nice To Haves

• Basic knowledge of formal verification methodology
• Some experience with power-aware (UPF) or similar verification methodology
• Some working experience using LLMs for efficiency and quality

Responsibilities

• establishing DV methodology
• test-plan development
• verification environment development including stimulus and checkers
• test-writing
• debug
• coverage
• sign-off for RTL freeze and tape-out
• developing detailed test and coverage plans based on the micro-architecture
• developing verification methodology suitable for the IP, ensuring a scalable and portable environment
• develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage
• develop verification plans for all features under your care
• execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures
• develop block, IP and SoC level test-benches
• track and report DV progress using a variety of metrics, including bugs and coverage

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level