Design Verification Engineer

Apple • Cupertino, CA

10h • Hybrid

About The Position

Apple Inc. is seeking a Design Verification Engineer to ensure bug-free first silicon for parts of the SoC/IP. The role involves developing detailed test and coverage plans based on the micro-architecture, and creating a scalable and portable verification methodology and environment. This includes developing stimulus, checkers, assertions, trackers, and coverage. Responsibilities also include developing verification plans for all features, executing these plans (including design and DV environment bring-up, regression, and debugging test failures), and developing block, IP, and SoC level test-benches. The engineer will track and report DV progress using metrics like bugs and coverage. Specific experience is required in pre-silicon Ser-Des (Serializer De-serializer) PHY verification of complex IO protocols like PCIe and USB4, developing verification environments for manufacturing screening DFT patterns, and developing post-silicon sequences from the verification environment for silicon validation reuse. The position is 40 hours/week.

Requirements

• Bachelor’s degree or foreign equivalent in Electronic Engineering, Electrical Engineering, or a related field
• 5 years of progressive, post-baccalaureate experience in the job offered or related occupation
• 3 years of experience with Performing Constraint Random Verification using Universal Verification Methodology (UVM)
• 3 years of experience Developing Verification Ips using System Verilog and Universal Verification Methodology (UVM)
• 3 years of experience Implementing System Verilog and System Verilog Assertions coding
• 3 years of experience Scripting using TCL/Perl or Python
• 3 years of experience in Microcontroller/CPU based SOC/IP verification
• 3 years of experience Implementing and verifying pre-silicon design to prototyping platforms like Emulation
• 3 years of experience Debugging pre silicon failures with industry standard tools like Verdi or Indago
• 3 years of experience in DFT verification with JTAG/1500 standards in pre-silicon environment to ensure Silicon can be debugged or brought up error free

Nice To Haves

• N/A

Responsibilities

• Ensure bug-free first silicon for part of the SoC / IP
• Develop detailed test and coverage plans based on the micro-architecture
• Develop verification methodology suitable for the IP, ensuring a scalable and portable environment
• Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage
• Develop verification plans for all features
• Execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features, and debug of the test failures
• Develop block, IP and SoC level test-benches
• Track and report DV progress using a variety of metrics, including bugs and coverage
• Work on pre-silicon ser-des(Serializer De-serializer )PHY verification of complex IO protocols like PCIe, Usb4
• Develop verification environment for manufacturing screening DFT patterns
• Develop post silicon sequences from verification environment for re-use for silicon validation

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• A range of discounted products and free services
• Reimbursement for certain educational expenses — including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs
• Discretionary restricted stock unit awards
• Purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees