Design Verification Engineer

Apple•Cupertino, CA

9h•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Build block/chip level testbenches using best-in-class verification methodologies. Create detailed verification plans from specifications in coordination with architects. Develop reusable block/IP level test benches and support IP integration verification. Generate directed and constrained random tests. Create and analyze coverage models and enhance testbenches/tests to increase coverage. Build automated flows for block and chip level verification. Debug failures, manage bug tracking, and close coverage. Hold detailed verification reviews and set standards for coding quality.

Requirements

Utilizing experience in Hardware Verification Language (HVL) and Hardware Design Language (HVL) including System Verilog or Verilog for Verification Environment and test development.
Utilizing experience with IP verification method and integration verification.
Utilizing knowledge of HVL methodology (UVM, OVM, or VMM) for constrained random test development.
Applying verification skills in problem solving, constrained random testing, and debugging.
Understanding of reusable verification framework to help speedup verification process.
Utilizing knowledge of digital logic design, chip architecture and microarchitecture to help analyze and debug RTL design.
Apply Industry standard protocol knowledge in developing monitor/checker and analyzing RTL design.
System Verilog Assertion (SVA) for verification.
Using Python/Perl scripts to develop verification test bench as well as post process verification results.
Defining coverage space and writing coverage model to measure verification quality and find verification holes.

Responsibilities

Build block/chip level testbenches using best-in-class verification methodologies.
Create detailed verification plans from specifications in coordination with architects.
Develop reusable block/IP level test benches and support IP integration verification.
Generate directed and constrained random tests.
Create and analyze coverage models and enhance testbenches/tests to increase coverage.
Build automated flows for block and chip level verification.
Debug failures, manage bug tracking, and close coverage.
Hold detailed verification reviews and set standards for coding quality.