Sr ASIC Design Engineer - TeraWave
About The Position
Blue Origin is hiring a Senior ASIC Design Engineer for its Silicon Systems Development team, supporting TeraWave, a satellite communications network designed to provide symmetrical data speeds of up to 6 Tbps. This foundational role contributes to the development of space-based communications technology. The position is onsite in Cupertino, California; San Diego, California; or Austin, Texas. A temporary remote-work exception is approved while the San Diego and Austin sites are being developed. The engineer will design and implement FPGA, digital ASIC, and/or mixed-signal ASIC solutions, develop verification approaches, perform design analyses and signoff, collaborate across engineering teams, and assist with lab integration and troubleshooting.
Requirements
- At least 7 years of experience in ASIC design and implementation.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Experience with FPGA and ASIC design.
- Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog.
- Experience with a Linux development environment.
- Experience with design verification and test bench development.
Nice To Haves
- Advanced degree (MS or PhD) in Electrical Engineering, Computer Engineering, or a related field.
- Experience across the full ASIC/FPGA lifecycle, including architecture, design, simulation, verification, validation, integration, and test.
- Experience with Software-Defined Radio architectures, ADC/DAC, and/or DSPs.
- Knowledge of DSP and communications systems, including spread spectrum, forward error correction, and modulation types such as QPSK, QAM, PCM/FM, and PAM.
- Strong object-oriented programming and scripting skills, including Python, TCL, or Perl.
- Experience with physical design flows and industry-standard EDA tools.
- Experience with RTL2GDSII physical design and signoff flows.
- Knowledge of deep sub-micron FinFET and CMOS technologies.
- Experience with DFT/Scan/MBIST/LBIST methodologies.
- Experience mentoring junior engineers.
Responsibilities
- Design and develop FPGAs, digital ASICs, and/or mixed-signal ASICs.
- Implement designs using VHDL, Verilog, and/or SystemVerilog.
- Develop verification methodologies and test benches for block- and system-level verification.
- Create and execute test plans, develop test harnesses, and implement coverage models.
- Conduct timing analysis, noise analysis, and other signoff checks.
- Collaborate with systems, firmware, architecture, and product engineering teams.
- Support lab integration and troubleshooting activities.
- Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Basic and supplemental life insurance
- Paid parental leave
- Short- and long-term disability
- 401(k) with company match of up to 5%
- Education Support Program
- Stock options for regular employees working at least 20 hours per week
- Paid time off of up to four weeks per year, based on weekly scheduled hours
- Up to 14 company-paid holidays
- Depending on role type and job level, employees may be eligible for benefits and bonuses based on individual contributions or other factors; amounts and eligibility are not guaranteed.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
