Solutions Engineer - AE

Cadence Design Systems

18d • $162,400 - $301,600

About The Position

Cadence is seeking a highly motivated and experienced Solutions Application Engineer to support customers developing next-generation advanced packaging solutions, including 2.5D, 3D-IC, chiplet-based architectures, AI/HPC packages, and heterogeneous integration technologies. The role works directly with semiconductor companies, OSATs, foundries, and system companies to deploy and optimize Cadence Advanced Package 3D-IC design flows. It combines technical expertise, customer engagement, solution development, and collaboration with R&D to drive customer success and product adoption.

The position is listed for the United States and may be remote or hybrid. Travel is approximately 2% to 5%, depending on customer demand and business needs.

The annual salary range for California is $162,400 to $301,600. The role may also be eligible for incentive compensation, including bonus and equity. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Compensation may vary based on qualifications, skill level, competencies, and work location.

Requirements

• Bachelor’s degree in Electrical or Electronics Engineering, or a related discipline; a master’s degree is preferred.
• 10+ years of experience in semiconductor packaging, IC packaging, PCB, substrate, or interposer design.
• Strong knowledge of advanced package design methodologies, 2.5D and 3D-IC integration, chiplet-based architectures, package manufacturing and assembly processes, high-speed signal design, and power delivery networks.
• Experience performing package layout, routing, constraint management, and package signoff.
• Solid understanding of package stackups, bump planning, escape routing, and substrate technologies.
• Excellent customer-facing communication and presentation skills.
• Ability to work independently while collaborating across global teams.

Nice To Haves

• Experience with Cadence Integrity 3D-IC Platform.
• Experience with Cadence Sigrity and Clarity 3D Solver.
• Hands-on experience with Cadence Allegro X APD.
• Knowledge of UCIe, HBM, AI accelerator packaging, and heterogeneous integration.
• Experience supporting foundry and OSAT design flows.
• Understanding of semiconductor assembly, reliability, and manufacturing processes.

Responsibilities

• Provide technical leadership and application support for Cadence 3D-IC design solutions.
• Assist customers with advanced package architecture, design implementation, and methodology development.
• Develop and demonstrate complete packaging workflows for organic substrates, silicon interposers, wafer-level packaging, 2.5D and 3D-IC integration, and chiplet-based package architectures.
• Support customer evaluations, proof-of-concepts, benchmarks, and production deployments.
• Deliver technical presentations, product demonstrations, workshops, and training sessions.
• Collaborate with sales teams to identify opportunities and provide technical pre-sales support.
• Work with R&D to communicate customer requirements, enhancement requests, and new technology needs.
• Support design-signoff methodologies, including DRC/LVS, connectivity verification, electrical rule checking, thermal analysis, Signal Integrity (SI), and Power Integrity (PI).
• Develop best practices, application notes, reference flows, and customer success methodologies.
• Assist in defining future product direction for advanced packaging, 3D-IC, and chiplet technologies.

Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical plan options
• Dental plan options
• Vision plan options
• Potential bonus and equity incentive compensation

What This Job Offers

• Job Type: Full-time
• Career Level: Senior