SoC Principal Physical Design Engineer

Synopsys•Austin, TX

68d•$171,200 - $256,800•Onsite

About The Position

Synopsys is hiring a SoC Principal Physical Design Engineer to lead advanced-node SoC physical design and support semiconductor customers. The role involves taking full-chip and block-level designs from RTL through GDSII tapeout, developing implementation and signoff strategies that meet power, performance, and area (PPA) targets, and resolving complex design-closure challenges at 5nm, 3nm, and below. The engineer will work with customers, design teams, and applications engineers, provide technical guidance and workshops, and contribute feedback that informs Synopsys tool and methodology roadmaps. The role also includes mentoring engineers and developing automation and flows to improve design productivity. The preferred location is Austin, with Dallas, Phoenix, and Mountain View listed as alternate locations. The role is not remote-eligible. The position is an employee role. The U.S. base salary range is $171,200–$256,800; the role may also be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers health, wellness, and financial benefits, with details available from the recruiter.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
10 to 15+ years of hands-on ASIC or SoC physical design experience.
A proven track record of multiple successful tapeouts at advanced process nodes.
Deep expertise in floorplanning, power planning, place and route, clock tree synthesis, timing closure, and physical verification, including DRC and LVS.
Strong working knowledge of IR-drop analysis, electromigration analysis, and ECO methodologies for late-stage design fixes.
Proficiency in scripting languages including Python, Tcl, Perl, or shell for automation and flow development.

Nice To Haves

Experience with Synopsys tools such as Fusion Compiler, PrimeTime, IC Validator, StarRC, Formality, and PrimePower.
Familiarity with foundry technologies from TSMC, Samsung, or Intel and an understanding of technology at 5nm and below.

Responsibilities

Lead full-chip and block-level physical implementation from RTL through GDSII tapeout on advanced-node designs at 5nm, 3nm, and below.
Define and execute floorplanning, power planning, placement, clock tree synthesis, routing, and signoff strategies to meet PPA targets.
Drive timing closure, power optimization, congestion reduction, and area improvement using Fusion Compiler, PrimeTime, and StarRC.
Perform and review static timing analysis, ECO implementation, IR-drop analysis, electromigration checks, and physical verification using IC Validator.
Work directly with semiconductor customers to troubleshoot design challenges, enable customer success, and deliver technical workshops and methodology guidance.
Develop automation scripts and flows using Python, Tcl, and shell scripting to improve design productivity and methodology efficiency.
Use AI- and ML-based physical design technologies, including DSO.ai and Fusion Compiler optimizations, to accelerate closure and explore the design space.
Establish physical design methodologies and best practices that scale across large SoC programs and improve turnaround time.
Translate real-world design challenges into actionable requirements that inform Synopsys implementation and signoff tool roadmaps.
Mentor junior engineers and help strengthen technical capability across the team.
Drive automation and flow innovation to reduce manual effort, catch issues earlier, and make physical design more predictable.
Surface findings from advanced-node design work to inform foundry engagement and tool development.