As a member of Apple’s Low Power group within Silicon Technologies, the SoC Power Flow Methodology Engineer helps deliver technology and capabilities for low-power chip design. The role develops and enhances low-power flows, giving designers new power-domain capabilities for future chips. The engineer delivers automated solutions for the Silicon Engineering Power team and contributes to the architecture, implementation, and verification of low-power design and verification flows. The work includes creating flows and tools for power analysis, optimization, and verification that may be used during RTL construction and verification, synthesis, or place and route (P&R). The role also involves communicating with design teams to answer questions about materials and drive issues to resolution.
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Job Type
Full-time
Career Level
Mid Level