SoC Power Modeling Engineer

Apple • Austin, TX

4d

About The Position

As part of Apple’s Silicon Engineering group, the SoC Power Modeling Engineer models power dissipation for various system-on-chip (SoC) IPs, including AI/ML components, and models corresponding power rails, peak-current requirements, and voltage-frequency operating points for upcoming Apple SoCs. The role contributes to optimization of leading-edge chips for power efficiency and involves collaboration with architecture, design, thermals, PMIC, and system-design teams. It also partners with lab, silicon characterization and validation, and technology teams to correlate models with hardware data.

The engineer models power dissipation and power delivery, establishes voltages for IP DVFM states, models power dissipation for customer use cases, and works with technology, silicon validation, and product engineering teams to establish voltage-frequency design points before and after silicon. The position also works with power lab and test teams to correlate models to hardware data.

Requirements

• Bachelor’s degree in a relevant field.
• At least 3 years of relevant industry experience.

Nice To Haves

• 3 or more years of relevant experience.
• Programming skills and understanding of low-power digital design and power fundamentals.
• Understanding of SoC power modeling and current demand.
• Understanding of electrical properties of on-die PDN, power gating, package, and system power delivery.
• Scripting and data-analysis skills, and experience with EDA tools.
• Understanding of VLSI design flow and CMOS technology.
• Extensive background in electrical engineering.
• Ability to understand and model thermal control loops and throttling mechanisms.
• Familiarity with physical design tools for power optimization.
• Teamwork and excellent communication skills.

Responsibilities

• Model power dissipation and power delivery.
• Establish voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, compute (AI/ML) accelerators, media IPs, caches, and fabric.
• Model power dissipation for customer use cases.
• Work with Technology, Silicon Validation, and Product Engineering teams to establish voltage-frequency design points before and after silicon.
• Work with power lab and test teams to correlate models to hardware data.
• Collaborate with architecture, design, thermals, PMIC, and system-design teams on SoC power and current profiles and voltage-frequency operating points.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level