SoC Power Spec Engineer

Apple•San Diego, CA

About The Position

As part of Apple’s Silicon Engineering group, the SoC Power Spec Engineer models power dissipation across IPs, applications, and at the SoC and system levels, including AI/ML workloads. The role contributes to power-efficiency optimization of leading-edge chips used in Apple products and collaborates with architecture, SoC design, and system design teams. It also partners with lab and silicon characterization and validation teams to correlate power models with silicon data. The engineer works with architects, silicon design engineers, software developers, and other teams on silicon optimization and model-correlation efforts for mobile SoCs. Responsibilities include modeling power for SoC components and customer use cases, helping define SoC power targets and power delivery, and correlating models against silicon measurements.

Requirements

  • Bachelor’s degree in a relevant field.
  • At least 10 years of relevant industry experience.

Nice To Haves

  • Master of Science in Electrical Engineering (MSEE) preferred.
  • Deep knowledge of SoC architecture and power modeling.
  • Deep understanding of SoC building blocks, including CPU, GPU, caches, memory, and media IPs.
  • Skills in scripting and data analysis.
  • Understanding of VLSI design flow and CMOS technology, with an electrical engineering background.
  • Ability to understand and model thermal control loops and throttling mechanisms.
  • Strong teamwork and excellent communication skills.

Responsibilities

  • Model power dissipation at the SoC level for Neural Engines, CPUs, graphics, AI/ML compute accelerators, media IPs, caches, and fabric.
  • Model power dissipation for customer use cases.
  • Work with system designers, the technology team, Silicon Validation, and Product Engineering to define SoC-level power targets and power delivery.
  • Work with power lab and test teams to correlate models with silicon data.
  • Collaborate with architects, silicon design engineers, and software developers on silicon optimization and model-correlation efforts for mobile SoCs.
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