SOC Power Architect
About The Position
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Candidate will be responsible for developing next generation power and limits system. With HPC, AI, and automotive system become so compute intense, the thermal and electrical constrained performance is becoming the bottleneck. A new system needs to be defined to have maximum performance while meet the thermal and power envelop. A fast DCVS system is also needed to make the transient response of the power delivery system to be able to support high frequency CPU, GPU, and NSP. The candidate will be defining the power and limit system to have optimal system performance while enforce the thermal and electrical limits with minimum SW intervention. This role will require the candidate to understand and work on all aspects of power control and limits architecture, micro architecture and interactions with system, SW and product team.
Requirements
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- 10+ years of strong experience in power and limits system
- Familiar with UPF and power domain crossing
- Experience in low power design methodology and clock domain crossing designs
- Proficient in Perl, Python scripting
Nice To Haves
- Expertise in post-Si debug is a plus
Responsibilities
- Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products.
- Collaborate with cross-functional groups to determine product execution path.
- Develop next generation power and limits system.
- Define the power and limit system to have optimal system performance while enforce the thermal and electrical limits with minimum SW intervention.
- Understand and work on all aspects of power control and limits architecture, micro architecture and interactions with system, SW and product team.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Senior
